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Document Title: [GyrussMap.html (html file)]

Gyruss Memory Map

# this document is not going to be of much use to you unless you have
# the schematics and follow along.

# Gyruss ROM files from TANT archive
GYA-1.BIN  - 11J - CPU Z80, 8K, Addr 0000 - 1FFF
GYA-2.BIN  - 12J - CPU Z80, 8K, Addr 2000 - 3FFF
GYA-3.BIN  - 13J - CPU Z80, 8K, Addr 4000 - 5FFF
GY-5.BIN   - 18E - CPU 6809, 8K, Addr 0000 - 1FFF
GY-6.BIN   - 02H - Graphics ROM
GY-7.BIN   - 5B/6C - Graphics ROM, 8K Bank 1, MSB
GY-8.BIN   - 6B/7C - Graphics ROM, 8K Bank 0, MSB
GY-9.BIN   - 7B/8C - Graphics ROM, 8K Bank 1, LSB
GY-10.BIN  - 8B/9C - Graphics ROM, 8K Bank 0, LSB
GY-11.BIN  - 6A - Audio Z80, 8K, Addr 0000-1FFF
GY-12.BIN  - 8A - Audio Z80, 8K, Addr 2000-3FFF
GY-13.BIN  - 11H - Audio 8039, 4K, Addr 0000 - 0FFF

# Gyruss CPU board memory map, gleaned from the schematics ...
#

#Addr     Chip Loc  Romfile?   Description
#-------- ---- ---- ---------- -----------
0000-1FFF 2164 11J  GYA-1.BIN  8k EPROM
2000-3FFF 2164 12J  GYA-2.BIN  8k EPROM
4000-5FFF 2164 13J  GYA-3.BIN  8k EPROM
6000-7FFF 2164 14J  N/C        8k EPROM
8000-87FF 2128 17C             2KB RAM, shared w/6809
8800-8FFF                      aliased ram
9000-9800 2128 5J,3J,2J      6KB SRAM
A000
B000
C000
D000
E000
F000

#
# CPU Board custom "6809"
#
0000 \_ /VCOUNT = 0, R/O places contents of 819:825 on data bus
1000 /
2000 \_ /9IRQ = 0
3000 /
4000 \_ SRAM @ 14A,13A,12A,11A MUXED with sprite generator. Even / Odd
5000 /  Data is split between X and Y;  X related to cols, Y related to rows
6000 \_ /9ZRAM -- Accesses 2K shared memory between Z80 and 6809
7000 /
8000 \
9000  |
A000   \ _ Not mapped.
B000   /
C000  |
D000 /
E000 \_ Program ROM, 8k 2764 (E000 - FFFF)
F000 /

#
# Gyruss AUDIO board memory map
#
#
# Audio Processor Z80A at 3.57MHZ
#
#Addr     Chip Loc  Romfile?   Description
#-------- ---- ---- ---------- -----------
0000-1FFF 2164 6A   gya-1.bin  8K Audio ROM 1
2000-3FFF 2164 8A   gya-1.bin  8K Audio ROM 1
3000-5FFF 2164 9A   gya-1.bin  8K Audio ROM 1
6000-61FF 2114 5A/4A           2 x 1Kx4 SRAM
6200-7FFF                      ram aliasing
8000-9FFF LS374 5C             command latch from master Z80

A000-BFFF \
C000-DFFF  +------ Does not appear to be mapped
E000-FFFF /



#
# Audio processor I/O map
# I/O ports are aliased every 32 ports, i.e.: the top two bits are 
# ignored. 00==20==40 ... 10==30==50 ..
#
#Port   Chip   Loc     Description
#------ ------ ------- ---------------------------------------------------
00-02   8910   11D     AY-3-8910 PSG, IOB = output control 1
03                     
04-06   8910   12D     AY-3-8910 PSG, IOB = output control 2
05                     
08-0A   8910   10B     AY-3-8910 PSG, IOA = clock control ? 
0B                     
0C-0E   8910   9B      AY-3-8910 PSG
0F                     
10-12   8910   8B      AY-3-8910 PSG
13                     
14-17   8910   11D     Interrupt "Drum" chip (any value, any addr)
18-1B   8910   11D     "Drum" data; (valid commands listed below).
1C-1F		       

# on each of the PSG's: i
# PORT+0 = register select
# PORT+2 = write register
# PORT+1 = read register

#
# Audio processor "Drum" uP
# uses an 8039 with one of it's I/O ports connected up to an R2R ladder
# to be a cheap (and _very_forgiving_ DAC).
# Commands are written by the AudioZ80 to an I/O port (0x18), and then 
# another I/O port (0x14) causes an interrupt to the 8039.
#
#Command  Sound Generated
#-------  ---------------
00        Stops all sound
01        Bass Drum
02        Low Tom-Tom
03        Mid Tom-Tom
04	  High Tom-Tom
05        Crash Cymbal
06        High-Hat
07	  Wierd "Hum" noise

------------------------------------------------------

Latches / Registers on the CPU board

LS367 - 8x1 Addressable latch

Loc Chip    Addr                 Pin   R/W Label  Notes
--- ------- FEDC BA98 7654 3210  ----- --- ------ -----------------------------

3B  LS138   This chip is selected by:  118=L && AB14; it lives on AD bus.
            11.. ...0 0... ....  Y0    W/O AFR
            11.. ...0 1... ....  Y1    W/O (26)   "Sound On"
            11.. ...1 0... ....  Y2    W/O (32)   "Sound Data"
            11.. ...1 1... ....  Y3    W/O To LS367 @ 3B (See below)
	    
            11.. ...0 0... ....  Y4    R/O (33)   Read DIPSW 2
            11.. ...0 1xx. ....  Y5    R/O (27)   IOEN for control reads
            11.. ...0 100. ....        R/O        Read CONTROL0 (see below)
            11.. ...0 101. ....        R/O        Read CONTROL1 (see below)
            11.. ...0 110. ....        R/O        Read CONTROL2 (see below)
            11.. ...0 111. ....        R/O        Read DIPSW 1
            11.. ...1 0... ....  Y6    R/O (22)   Read DIPSW 3
            11.. ...1 1... ....  Y7    
	    
	    C000 - WR - AFR (watchdog of some kind, write to C000 
	    	   within 16 clocks of 816 (which seems to be hooked 
		   up to Z80 NMI through a flip flop, and is probably 
		   a vertical-blank interrupt)
	    C080 - WR - Sound on
	    C100 - WR - Sound data latch
	    C180 - WR - write 0 to clear NMI
	    C181 - WR - n/c
	    C182 - WR - Increment coin counter 1
	    C183 - WR - Increment coin counter 2
	    C184 - WR - n/c
	    C185 - WR - FLIP (used for page flipping or maybe COCKTAIL mode)
	    
	    C000 - RD - Read DIP 2
	    C080 - RD - Read CONTROL0 (see below)
	    C0A0 - RD - Read CONTROL1
	    C0C0 - RD - Read CONTROL2
	    C0E0 - RD - Read DIP 1
	    C100 - RD - Read DIP 3
	    C180 - RD - Unused.
	    
2B  LS367   This chip gets selected by output Y3 from the LS138 @ 3B
            (117=0, 118=0, AB14=1, AD8=1, AD7=1.  High Bit (IO8) is latched
	    on write).
	    
	    11.. ...1 1... .000 - Q0   /INTST INTerrupt STop (0 clears NMI)
	    11.. ...1 1... .001 - Q1   (25)   Not connected?
	    11.. ...1 1... .010 - Q2   (24)   ->coin counter 1
	    11.. ...1 1... .011 - Q3   (23)   ->coin counter 2
	    11.. ...1 1... .100 - Q4
	    11.. ...1 1... .101 - Q5   FLIP   ???
	    11.. ...1 1... .110 - Q6
	    11.. ...1 1... .111 - Q7
	    
	    See above for memory mapped addresses.
	    
	    
Register Bits Description
-------- ---- --------------------------------------------------------------
CONTROL0  0   COIN1
          1   COIN2
	  2   SERVICE
	  3   1P-START
	  4   2P-START
	  5   N/C reads as 1
	  6   N/C reads as 1
	  7   N/C reads as 1
CONTROL1  0   1P-LEFT
	  1   1P-RIGHT
	  2   1P-UP
	  3   1P-DOWN
	  4   1P-SHOOT1
	  5   1P-SHOOT2
	  6   2P-SHOOT3
	  7   N/C reads as 1
CONTROL2  0   2P-LEFT
	  1   2P-RIGHT
	  2   2P-UP
	  3   2P-DOWN
	  4   2P-SHOOT1
	  5   2P-SHOOT2
	  6   N/C reads as 1
	  7   N/C reads as 1
	  
	 
Numbered Signals

Num   Description
----- --------------
117   = Z80 Write  ???
118   = !AB15 ???
815   originates from 11G:15
817   Sync; originates in 11G:17 (marked 082)
819   originates from 11G:19, buffered in 10E onto 9DB7
820   originates from 11G:20, buffered in 10E onto 9DB6
821   originates from 11G:21, buffered in 10F onto 9DB5
822   originates from 11G:22, buffered in 10F onto 9DB4
823   originates from 11G:23, buffered in 10F onto 9DB3
824   originates from 11G:24, buffered in 10F onto 9DB2
825   originates from 11G:25, buffered in 10F onto 9DB1
826   originates from 11G:26, buffered in 10F onto 9DB0

Named Signals

Name   Description
------ --------------
/9ZRAM multiplexed with /RW1 to enable read on 2128 SRAM @ 17C
/CRWR  read/write enable for 2128 SRAM @ 17C
/Z09EN multiplexed with /9ZRAM to chip-select 2128 SRAM @ 17C



Bus multiplexers
----------------
19B/18B/17B/17A   A = 6809 A0:10, /9ZRAM, /Z09WR
                      Y = AF0:6,   /CRCS, /CRWR
                  B = Z80 A0:A10, /Z09EN, /RW1
		  Selected by /803