Document Title: [instnote.txt (text file)]

Notes on G65SC802/816 Instructions

All Opcodes Function in All Modes of Operation

It should be noted that all opcodes function in all modes of operation.
However, some instructions and addressing modes are intended for G65SC816
24-bit addressing and are therefore less useful for the G65SC802. The
following is a list of Instructions and addressing modes which are primarily
intended for G65SC816 use:

	JSL; RTL; [d]; [d],y; JMP al; JML; al; al,x

The following instructions may be used with the G65SC802 even though a
Bank Address is not multiplexed on the Data Bus:

	PHK; PHB; PLB

The following instructions have "limited" use in the Emulation mode.

* The REP and SEP instructions cannot modify the M and X bits when in the
Emulation mode. In this mode the M and X bits will always be high (logic 1).

* When in the Emulation mode, the MVP and MVN instructions only move data
in page zero since X and Y Index Register high byte is zero.


Indirect Jumps

The JMP (a) and JML (a) instructions use the direct Bank for indirect
addressing, while JMP (a,x) and JSR (a,x) use the Program Bank for indirect
address tables.


Switching Modes

When switching from the Native mode to the Emulation mode, the X and M bits
of the Status Register are set high (logic 1), the high byte of the Stack is
set to 01, and the high bytes of the X and Y Index Registers are set to 00.
To save previous values, these bytes must always be stored before changing
modes. Note that the low byte of the S, X and Y Registers and the low and high
byte of the Accumulator AL and AH are not affected by a mode change.


WAI Instruction

The WAI instruction pulls RDY low and places the processor in the WAI
"low power" mode. /NMI, /IRQ or /RESET will terminate the WAI condition and
transfer control to the interrupt handler routine. Note that an /ABORT input
will abort the WAI instruction, but will not restart the processor. When the
Status Register I flag is set (IRQ disabled), the IRQ interrupt will cause the
next instruction (following the WAI instruction) to be executed without going
to the IRQ interrupt handler. This method results in the highest speed response
to an IRQ input. When an interrupt is received after an ABORT which occurs
during the WAI instruction, the processor will return to the WAI instruction.
Other than RES (highest priority), ABORT is the next highest priority, followed
by NMI or IRQ interrupts.


STP Instruction

The STP instruction disables the Phi2 clock to all circuitry. When disabled,
the Phi2 clock is held in the high state. In this case, the Data Bus will
remain in the data transfer state and the Bank address will not be multiplexed
onto the Data Bus. Upon executing the STP instruction, the /RES signal is the
only input which can restart the processor. The processor is restarted by
enabling the Phi2 clock, which occurs on the falling edge of the /RES input.
Note that the external oscillator must be stable and operating properly before
RES goes high.


Tranters trom 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers

All transfers from one register to another will result in a full 16-bit output
from the source register. The destination register size will determine the
number of bits actually stored in the destination register and the values
stored in the processor Status Register. The following are always 16-bit
transfers, regardless of the accumulator size:

	TCS; TSC; TCD; TDC


Stack Transfers

When in the Emulation mode, a 01 is forced into SH. In this case, the B
Accumulator will not be loaded into SH during a TCS instruction. When in the
Native mode, the B Accumulator is transferred to SH. Note that in both the
Emulation and Native modes, the full 16 bits of the Stack Register are
transferred to the Accumulator, regardless of the state of the M bit in the
Status Register.

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