Document Title: [Boris - Converting Schematics to an Emulator V1.2.html (html file)]
Converting Schematics to an Emulator V1.2 by Daniel Boris (email@example.com) 5/9/98 Table of Contents 1.0 Introduction 2.0 Zarzon Hardware 2.1 Introduction 2.2 Processor 2.3 Memory Map 2.4 Roms 3.0 Video Section 3.1 Video RAM 3.2 CRT controller 3.3 Video Shifter 3.4 Color Selector 3.5 Putting all together 4.0 Sound (to be added later) Appendix 1: Converting Binary to Hex 1.0 Introduction The purpose of the document is to explain the basic process for extracting the information necessary to write an emulator (or MAME driver) from schematics of an arcade machine. I will be using the game Zarzon as an example. It is best that you follow along with the schematics as you read this document. You can get the schematics at: http://www.spies.com/arcade/bronzeage/ You may also wish to download the ROM images for the game, they can be found at: ftp://ftp.tant.com/incoming (They may eventually be moved into the main archive) NOTE: I have made ever attempt to be sure this document is accurate, but it is inevitable that some mistakes have slipped through. Use this info at you own risk. I tried to keep this document as simple as possible but to fully understand it you should have a basic knowledge of digital electronics. You should also have a working knowledge of binary numbers. I will refer to signals as being high or low, high=1 and low=0 in binary. 2.0 Zarzon's Hardware 2.1 Introduction There are 2 boards in this game and 3 pages of schematics for each so I will refer to the pages as CPU1, CPU2, CPU3, CRT1,CRT2,CRT3. Chips are all numbered on the schematics, these numbers appear within the box of each chip. The same numbers are used on both boards so chip 8 on the CPU board is not the same as chip 8 on the CRT board. The CPU board contains the processor, RAM, ROM, address decoding, and the sound hardware. The CRT board contains the video circuitry, and I/O ports. Interconnections between the boards ae shown as rectangles with rounded ends and a number and letter inside. Connections that go off the boards to other parts of the machine (like the power supply or control panel) are shown as circles with a number inside. You can determine where these connections go by looking at the wiring diagram in the manual. 2.2 Processor The first step is to determine what processor(s) the board uses. This is pretty easy on Zarzon, on page CPU1 the CPU (chip 11) is clearly marked as a 6502. To determine the speed of the processor we look at pin 37 which is the clock input to a 6502. That signal is generated by the clock circuit in the upper left corner of page CPU1. It starts with an 11.289Mhz oscillator, which enters the clock input of chip 34 (74LS163). This chip is a counter and is used to divide down the input clock. The clock comes out of pin 11 (QD) which is the divide by 16 output, so the processor clock = 11.289Mhz/8 = .705562Mhz. The IRQ input to the processor goes over to page CRT2 chip 80. This chip is a latch, when input A goes high the output will stay high until it is cleared by a pulse on pin 5 (I will talk more about this part later). The A input is connected to chip 2 on page CRT3. It is connected to the V-SYNC output of chip 2 which is a CRT controller chip. V-SYNC happens at the end of each frame of video and signals the start of vertical blank (the time it takes for the CRT's electron beam to go from the bottom right of the screen back to the top left). The NMI input to the processor goes to page CPU3 where is comes through chip 27 from input 15. This input is connected to the coin input on the machine (see the wiring diagram), so that whenever a coin is inserted it generated an NMI. 2.3 Memory Map The next step is to work out the memory map for the board. The memory map is a list of where each device in the system (RAM, ROM, I/O ports, etc) are located in memory. To work out the memory map we must first find the address decoder, this can be found in the upper left corner of page CPU2. The first decodes to look at are the ones for the code ROMS, these are labeled ROM1 through ROM12 and these are connected to the CS pins on the ROMS on page CPU1. When any one of these signals goes low then the corresponding ROM will be enabled. All of these inputs come out of chip 12 (LS154) which is a decoder IC. For the LS154 to be enabled, pins 18 and 19 (which in this case are connected together) must be low. This input comes through the inverted 27, from the XOR gate 30. (A quick sidebar: Gate 30 demonstrates one of the pitfalls of decoding schematics. If you don't look closely at the schematics it may appear that Gate 30 was an OR gate, but if you look at the chips number 74LS86 it turns out to be an XOR. I did not realize this until I tried decoding another part of the circuit and it just wasn't making sense. So be careful when reading the schematics) The inputs to the XOR gate are A14 and A15 which are address lines from the CPU, so when ever A14 OR A15 is high (but not both), the LS154 will be enabled. Once the LS154 is enabled, one of it's 15 outputs will go low. Which output goes low will be determined by the inputs labeled A,B,C,D which are connected to A11,A12,A13,A15. If they are all low then output 0 (ROM1) will go low, if A12 goes high the inputs represent a binary 2, so output 2 (ROM3) goes low. Lets write up a table to make this a little more clear: Address bit 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 1 0 0 0 x x x x x x x x x x x ROM1 To figure out ROM1 we know that A11,A12,A13,A15 have to all be 0, so we put those in the table. If A15 is 0 then the only way for chip 12 to be enabled is to have A14 be a 1. A10..A0 are all market x (don't care) since they have no bearing on this decode. To figure out what address range this represents let x = 0 and convert from binary to hex, which is $4000. Next let x = 1 and convert to hex again, which is $47FF. So we now know that ROM1 is enabled when the address is in the range $4000-$47FF. Lets do a table for the rest of the ROM enables: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 1 0 0 0 x x x x x x x x x x x ROM1 $4000-$47FF 0 1 0 0 1 x x x x x x x x x x x ROM2 $4800-$4FFF 0 1 0 1 0 x x x x x x x x x x x ROM3 $5000-$57FF 0 1 0 1 1 x x x x x x x x x x x ROM4 $5800-$5FFF 0 1 1 0 0 x x x x x x x x x x x ROM5 $6000-$67FF 0 1 1 0 1 x x x x x x x x x x x ROM6 $6800-$6FFF 0 1 1 1 0 x x x x x x x x x x x ROM7 $7000-$77FF 1 0 0 0 0 x x x x x x x x x x x ROM9 $8000-$87FF 1 0 0 0 1 x x x x x x x x x x x ROM10 $8800-$8FFF 1 0 0 1 0 x x x x x x x x x x x ROM11 $9000-$97FF 1 0 0 1 1 x x x x x x x x x x x ROM12 $9800-$9FFF You will notice that we skipped ROM8, this is because that output on chip 12 does not go directly to the ROM8 signal, it passed through some other logic first. Lets look at a table again to see why this is: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 1 1 1 1 x x x x x x x x x x x chip 12 pin 8 low If we now work out the logic for the 3 NAND gates (chip 6) we find that ROM8 goes low, so ROM8 will be enabled at address range $7800-$7FFF. But if this where all there is to it, then we would not need the NAND gates so there must be something else going on. Lets look at another condition: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 1 1 x x x x x x x x x x x x x x This will also set ROM8 low, and since both A14 and A15 are high, chip 12 will NOT be enabled because of the XOR gate so we ignore all the other addresses. So ROM8 will also be enabled at the range $C000-$FFFF. Why is this done? The 6502 fetches it's reset and interrupt vectors from locations $FFFA-$FFFF, so there must be a ROM in that area. This little circuit causes the ROM connected to ROM8 to be enabled both at $7800-$7FFF and $F800-$FFFF. Next lets look at Chip 5 which is another decoder. This decoder is enabled whenever pins 4 and 5 are low and 6 is high. 6 is tied to +5V so it is always high and pin 5 is connected to A13. Pin 4 is connected through chip 27 to chip 31 in such a way that it will only be low when A14 and A15 are both low. Time for another table: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 0 0 x x x x x x x x x x x x x $0000-$1FFF Chip 5 enabled The outputs on chip 5 work the same way as chip 12, inputs A,B,C (A10,A11,A12) select which output goes low: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 0 0 0 0 0 x x x x x x x x x x $000-$3FF Y0 0 0 0 0 0 1 x x x x x x x x x x $400-$7FF Y1 0 0 0 0 1 0 x x x x x x x x x x $800-$BFF Y2 0 0 0 0 1 1 x x x x x x x x x x $C00-$FFF Y3 0 0 0 1 0 0 x x x x x x x x x x $1000-$13FF Y4 0 0 0 1 0 1 x x x x x x x x x x $1400-$17FF Y5 0 0 0 1 1 0 x x x x x x x x x x $1800-$1BFF Y6 0 0 0 1 1 1 x x x x x x x x x x $1C00-$1FFF Y7 Unfortunately the labels are not real helpful so we will have to trace them to see what each one does: Y0: This goes to CPU1 Chip 21 which is a RAM chip. You will notice that there are only 8 address inputs to this chip (A0..A7), so there are only 256 bytes of RAM here. The ram would then be at $00-$FF, and that same block of RAM would also appear at $100-$1FF, $200-$2FF and $300-$3FF. This is known as mirroring memory. Most of the time it is not necessary to emulate the mirroring but in this case it is important. In a 6502 system the memory at addresses $00-$FF is called the zero page and can be accessed faster then other sections of memory, so this region is used to store commonly used data. The memory at addresses $100-$1FF is the 6502's stack space. Since both of these areas are very important to the 6502's operation we can be pretty sure that they are both used, so we must implement the mirroring. Y1..Y7: These all go to the CRT board and are used to enable the video memory, for the moments lets just say that $400-$1FFF is video RAM. The next section of address decoding is on page CRT1 in the lower left corner. Chip 20 (74LS155) is a dual decoder meaning it has 2 separate decoding sections in one chip. Section 1 is enabled when pin 1 (A2) is high and pin 2 is low. Section 2 is enabled when pin 15 (A2) is low and pin 14 is low. Pins 14 and 2 are connected to chip 42 (OR gates), such that 14 will go low when the processor is reading and 2 will go low when the processor is writing. Also going into these OR gates is the signal 02 (Phase 2). They did something a little tricky here. If you look at the schematics 02 is connected to a flag labeled 2-V. These flags designate connections between the 2 boards. The corresponding flag on the CPU board in on page CPU2. It goes through gates 26 and 31 and back to the address decoder 12 pin 16. If you work out the logic you can determine that the decoders on the CRT board can only be enabled when pin 16 of chip 12 is low. Table time: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 1 0 1 1 0 x x x x x x x x x x x $B000-$B7FF The decoder on the CRT board will only be enabled in the address range $B000-$B7FF. Now we can build a table for decoder 20 on the CRT board: R/W 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 W 1 0 1 1 0 x x x x x x x x 1 0 0 $B004 W 1 0 1 1 0 x x x x x x x x 1 0 1 $B005 W 1 0 1 1 0 x x x x x x x x 1 1 0 $B006 W 1 0 1 1 0 x x x x x x x x 1 1 1 $B007 R 1 0 1 1 0 x x x x x x x x 0 0 0 $B000 R 1 0 1 1 0 x x x x x x x x 0 0 1 $B001 R 1 0 1 1 0 x x x x x x x x 0 1 0 $B002 R 1 0 1 1 0 x x x x x x x x 0 1 1 $B003 You will notice that in this situation I ignore the x's. These are decodes for I/O so the address range is not important. The program normally only uses the first address in the range (be careful because sometimes this is not the case). The enables on the schematics are actually named with the addresses (B000, B001, etc) so it is pretty safe to assume that these are the correct addresses. Now we can trace these and see what they do: B000, B001: These go back to page CPU3 and connect to latches 46, 45. These latches control the sound section of the board. B002: This goes to chip 18 on CRT2. This latch only uses 2 bits, D0, D1. D0 - This signal goes into the video section. D1 - This goes to chip 80 which controls the IRQ to the CPU. D1 is used to clear the IRQ. B003: This goes to chip 15 on CRT2 and is used to latch D0 and D1 onto signals BACK1 and BACK2. These might control the background color. B004: This signal controls chip 5 on CRT2 and is used to read inputs. To figure out where these inputs come from trace the flags to page CPU3 where they connect to circled numbers. The numbers can be found on the Wiring Diagram (Figure 9 in the manual), on the block labeled CPU PC Board ASSY. Here are what the bits do: D0 = Left mov D1 = Right mov D2 = Fire D3 = No connection D4 = No connection D5 = No connection D6 = Beam D7 = 2P Sel D0,D1,D2,D6,D7 are all switches, the are low when pressed, high when no pressed. D3,D4,D5 are not connected to anything and are always high. B005: This signal controls chip 6 on CRT2. This works the same way as B004. The signals are as follows: D0 = 1P Sel D1..D7: Seem to be unconnected B006: This signal controls chip 7 on CRT2. This latches is connected to a dip switch. B007: This signal controls chip 8 on CRT2. The bits have the following functions: D0 = NMI. The bit shows the current state of the NMI signal. This signal comes from page CPU3 and is controlled by the coin input of the machine. When a coin is inserted this bit goes low and a non-maskable interrupt is generated to the processor. D1..D3 = Unused D4..D7 = These inputs are connected to the counter chip 19, which is constantly clocked by the signal F1. This is probably used to generate random numbers. There is one last piece of address decoding on page CRT3. Chip 2 is a CRT controller chip and it has configurable registers in it. It is enabled by the CS input on pin 25. Chip 2 will be enabled when all 3 inputs to chip 78 are high. The flag "1-2" goes to page CPU2 where it goes into NOR gate 31. Here is the table for this decode: 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 0 0 1 1 x x x x x x x x x x x x $3000-$3FFF Now we can collect up all this info into a full memory map: 0000 - 00FF RAM 0100 - 01FF Mirror of RAM 0000-00FF 0200 - 02FF Mirror of RAM 0000-00FF 0300 - 03FF Mirror of RAM 0000-00FF 0400 - 1FFF Video RAM 3000 - 3FFF CRT controller 4000 - 47FF ROM1 ZARZ122.07 4800 - 4FFF ROM2 ZARZ123.08 5000 - 57FF ROM3 ZARZ124.09 5800 - 5FFF ROM4 ZARZ125.10 6000 - 67FF ROM5 ZARZ126.13 6800 - 6FFF ROM6 ZARZ127.14 7000 - 77FF ROM7 ZARZ128.15 7800 - 7FFF ROM8 ZARZ129.16 8000 - 87FF ROM9 ZARZ130.22 8800 - 8FFF ROM10 ZARZ131.23 9000 - 97FF ROM11 ZARZ132.24 9800 - 9FFF ROM12 Unused B000 - B001 Sound B002 0 = Flip screen (?) 1 = Clear IRQ B003 0,1 = Background color (?) B004 D0 = Left mov D1 = Right mov D2 = Fire D3 = No connection D4 = No connection D5 = No connection D6 = Beam D7 = 2P Sel B005 D0 = 1P Sel D1..D7: Seem to be unconnected B006 Dip Switch B007 D0 = Coin D4-D7 = Random number (?) F800 - FFFF Mirror of 7800 - 7FFF ROM ZARZ129.16 2.4 Roms Now that we have a memory map for the game we want to take a look at the roms. The following rom image are found in the romset: ZARZ122.07 ZARZ123.08 ZARZ124.09 ZARZ125.10 ZARZ126.13 ZARZ127.14 ZARZ128.15 ZARZ129.16 ZARZ130.22 ZARZ131.23 ZARZ132.24 ZARZ133.53 ZARZ134.54 ZARZ135.73 ZARZ136.75 You will notice that the 2 digit numbers at the end of the name correspond to the chip numbers on the schematics, this makes matching them up very easy. On page CPU1 there are 12 ROMS, these are numbered 7,8,9,10,13,14,15,16,22, 23,24,25. These roms contain the program code for the machine. We have the first 11 ROMS, but the 12th (chip 25) is missing. It is not unusual to find incomplete rom sets on the internet, but in this case it turns out that the there is actually nothing missing. I talked to someone who had the board an he told me that socket 25 is empty on the board. Why would this socket be empty? There could be a few reasons. First it is possible that the hardware was "over designed". They may have put room for more program code then was actually needed. It is also possible that this board is used in more then one game and that the socket is used in a different game. The next 2 roms (53,54) can be found on page CPU2. It may not be immediately obvious, but this is the section of the circuit that generates the sounds for the game. The final 2 roms (73,75) can be found on page CRT1. These roms are in the video section and probably contain graphic shape data. Again you will notice two missing roms (74,76), and it turns out that these sockets are also empty on the board. If you look at the output enable (OE) pins on these roms you will see that they goto connector 2-21, then to page CPU3 where they are connected to one of the outputs of latch 45. This means that the processor can set the state of this signal, and thus select one bank or graphics roms or the other. It is possible that the designers of the game intended to use two sets of graphics but for some reason ended up using only one. 3.0 Video Section Figuring out the video section is a little more complicated then figuring out the memory map. We will look at the video section piece by piece, but we will not be able to work out it's total functioning until we put all the pieces together. 3.1 Video RAM In the memory map section above we determined that the video RAM was at addresses $0400-$1FFF. Now lets take a closer look at the video RAM to see how it is accessed. There are two blocks of video RAM on the CRT board. The first is on page CRT1 and is composed of chips 48,49,50,51,52,53,54,55. The second is on page CRT3 and is composed of chips 32,33,34,35,36. First lets look at the ram on page CRT3. If you look at the chip select inputs (CS) you can see that RAMS 32 and 33 are tied together, and 34 and 25 are tied together. Since these are 4-bit RAMS, 32 and 33 are tied together to form an 8-bit RAM, the same with 34 and 35. Chip 36 is not tied to any of the others so it remains a 4-bit RAM. Following these CS inputs it can be seen that they come out of chip 57, AND gates. One input of each of these gates is connected to Y1,Y2, and Y3 which we know are address decodes. The other inputs of the AND gates are connected to a signal called 02. This signal come from the processor and when it is high it indicates that the processor is trying to access the bus. When the processor is not accessing the bus, 02 is low which causes the outputs of the and gates to go low and this enables all the rams onto the bus. When the processor is accessing the bus 02 is high so when either Y1, Y2, or Y3 go low it will enable the corresponding RAMS. Next lets look at the data bus going to each of the rams. The bus is labeled RD1-0..7, RD2-0..7, and RD3-0..3, and are collectively called the RAM DATA BUS. To be able to write to these RAMS the processor must have access to this bus. If you look at page CRT2 you will see 5 chips labeled 43,44,45,46,47, this is where the processor DATA BUS connects to the RAM DATA BUS. When pin 1 on these chips is low data is allowed to flow from the RAM side of the chip to the processor side. When pin 19 is low data is allowed to flow from the processor side to the RAM side. Above these chips is a group of logic gates that determine how they are enabled. If you work out the logic you determining that when Y1 is low, the processor can read and write to the RD3 RAM, when Y2 is low, the processor can read and write to the RD2 RAM and when Y3 is low the processor can read and write to the RD1 RAM. $400-$7FF Y1 RD1 RAM $800-$BFF Y2 RD2 RAM $C00-$FFF Y3 RD3 RAM (bits 0..3 only) Now lets see where this data goes so we can determine what it does. RD3 goes through chip 61 on page CRT3 to signals labeled 2C1,2C0,1C0,1C1. These goto the circuit in the lower left corner of page CRT3 which is a color encoding circuit. This circuit determines which color gets displayed at each point on the screen, so RD3 has something to do with controlling colors. RD2 goes through chip 60 on page CRT3 to a buss called the ROM ADDRESS BUS (RA0..7). This bus goes over to page CRT1 and connects to the graphics roms 73,74,75,76. RD2 will thus be used to select which graphics character is displayed at each point on the screen. RD1 goes through chip 58 on page CRT1. This bus connects to the address inputs of the second section of video RAM. We will talk about this more later on. Finally we need to look at the address inputs to these RAMS. The address bus is called RA0 and it connects to chips 21,22, and 23 which are multiplexer chips. These chips allow the RA0 bus to be connected to one of 2 sources. The first source is the processor address bus, and the second source is the video controller (chip 2). This is a very common arrangement. Part of the time the processor is connected to the RAMS so they can be read and written, the other part of the time the RAMS are connected to the video controller so that the data to build the display can be read out. Now lets look at the other section of video RAM, this can be found on page CRT1. This RAM is composed of chips 48 through 55. If you look at the way the chips are wired you will see something a little odd. The RAMS are connected together in pairs, chips 48 and 50, 49 and 41, etc. Every signal on one chip in the pair is connected to the same signal on the other. This seems to be an error in the schematics. I believe the data buses on the RAM chips should be like this: 48 - SH1-0,SH1-1,SH1-2,SH1-3 50 - SH1-4,SH1-5,SH1-6,SH1-7 49 - SH1-0,SH1-1,SH1-2,SH1-3 51 - SH1-4,SH1-5,SH1-6,SH1-7 52 - SH2-0,SH2-1,SH2-2,SH2-3 54 - SH2-4,SH2-5,SH2-6,SH2-7 53 - SH2-0,SH2-1,SH2-2,SH2-3 55 - SH2-4,SH2-5,SH2-6,SH2-7 Once again lets start by looking at the chip selects. The CS inputs are connected to CS1, CS2, CS3, and CS4. These come out of chip 67 which is a multiplexer chip. The B inputs to this chip come from Y4,Y5,Y6, and Y7 which we know are enables from the memory map: $1000-$13FF Y4 RAM 48,50 $1400-$17FF Y5 RAM 49,51 $1800-$1BFF Y6 RAM 52,54 $1C00-$1FFF Y7 RAM 53,55 The data bus from these RAMs is connected to two buses. If you trace these busses you will see that they first go to chips 25,26,27, and 28. These chips simply allow the processor to read and write to these RAMS. These buses also go over to page CRT2 and connect to chips 37,38, 39 and 40 which are shift registers. We will talk more about this section later on. Now for the address bus. The address input to these RAMs connects to the bus labeled RA0..9. This bus comes from the multiplexer chips 59,71 and 72. As usual one of the inputs to the multiplexers comes from the processor address bus. The other set of inputs to the multiplexers comes from 2 different places. Bits 3..9 come from chip 58 which we learned earlier come from the first set of video RAMS. Bits 0..2 come from signals RA0..RA2 which come from the CRT controller. 3.2 CRT controller The next piece of the puzzle to look at is the CRT controller on page CRT3. It is unusual to see a stock CRT controller in older arcade games. Usually the functions that this chip provides are implemented in discreet logic. The chip is labeled HD46505S. I was not able to find any information on this chip, but the pinouts match a MC6845 so I am assuming it is the same chip. The CRT controller is responsible for generating all the display timing and the addresses that are used to read the video memory. The CRT controller is attached to the CPU so that it's internal registers can be setup. The registers control how the chip draws the screen. In an arcade game it is very possible that this chip is configured once and this configuration is never changed during the game. If this is the case then it may not be necessary to emulate the internal registers of this chip. Zarzon, like a lot of arcade games, uses a character based display. The screen is divided up into individual characters. Each character is usually 8 pixels wide by 8 pixels high. A lot of machines use a display that is 32 characters wide by 32 characters high. The memory outputs, which are labeled MA0-MA9, and RA0-RA2, are used to address the video memory and to determine what character should be display at each location on the screen. The MA0-MA9 outputs are the video ram address to read each character from. This address is 10 bits wide. If we divide that in half we get 5 bits, which i in binary can give you the maximum value of 32. So this game uses 5 bits for the horizontal screen positions, and 5 bits for the vertical thus giving us the standard 32x32 character screen. The RA0-RA2 is the line counter out put. As I said earlier, it's very common for characters to be 8 pixels high, so the RA0-RA2 outputs are used to select which scanline of each character to draw. You will notice that all the video ram addresses from the CRT controller go through exclusive OR gates. The second input on each gate is connected to a signal called SGN. When SGN is high, every address input will be inverted (0 will become 1 and 1 will become 0). The purpose of this is to implement a "cocktail flip". What is "cocktail flip"? Some arcade machine were designed to be built as cocktail table units as well as normal machines. On a cocktail table game the 2 players sat opposite each other on either side of the machine, and the screen would flip for each player. When SGN goes high all the video addresses will be inverted which will flip the screen both horizontally and vertically. The final part of the CRT controller circuit is chip 12 which is an adder. When SGN is low, signals MA7,MA8,MA9 just get passed from the inputs to the outputs. When SGN is high, 1 is added to the binary value of MA7-MA9, and passed through to the output. I am not sure of the exact purpose of this circuit. 3.3 Video Shifter The data that comes out of the character roms and the video RAM comes out 8 bits at a time. The video image is draw 1 bit (pixel) at a time so the 8 bits must be fed to the video output 1 bit at a time, this is the job the video shifter. The shifter is composed of 8 shift register ICs on page CRT2 numbered 37,38,39,40,62,63,64, and 65. The shifter register ICs take 8-bit parallel data as an input and shift it out onto the QH output one bit at a time. These chips are connected together in pairs. Although it is not clear on the schematics I am pretty sure the second chip in each pair is hooked up with the data bus reversed from the first. For example: Chip 37, D0 = SH1-0, D7=SH1-7 Chip 38, D0 = SH1-7, D7=SH1-0 The purpose of this would be to complete the cocktail flip that we discussed in the last section. There are 4 sets of shift registers, the first set connects to the SH1 bus, the second to the SH2 bus, the third to the OD1 bus and the fourth to the OD2 bus. The serial outputs from these shifter chips go into chip 66 which is a data selector. The state of pin 1 (SGN) determines if the A or B inputs get connected to the outputs. The SGN signal is used to select between one or the other of the shifters in each pair. The 4 serial outputs from each of the buses end up on signals 1Y, 2Y, 3Y, and 4Y. 3.4 Color Selector In the lower left corner of page CRT3 is the color selector circuit. The purpose of this circuit is to generate the proper RGB (Red,Green,Blue) voltage levels for each pixel on the screen. Lets work through the circuit backwards starting from the RGB outputs. The labels 2-8, 2-J, 2-9 are the RGB outputs that eventually go to the CRT. These outputs are analog signals that determine the intensity of each color at each point on the screen. The higher the voltage on each pin the brighter that color will be in the final pixel on the screen. These outputs are connected through resistors to chip 3 which is the palette ROM. The resistors form a digital to analog converter. The R and G outputs of the ROM have 3 bits each so they can produce 8 different voltage levels on the output. The B outputs of the ROM have only 2 bits so this can only produce 4 voltage levels. Each byte in the palette ROM specifies a different color, or palette entry. The 5 address inputs to the ROM determine which palette entry will be used at each point on the screen. The CS input to the ROM enables the outputs when it is low. This signal goes through IC 14 which is a latch to the signal called BLANK. BLANK is generated by the CRT controller chip and goes high during the horizontal and vertical blank time. This turns off the palette ROM which disables the output to the CRT. Next look at the address inputs to the palette ROM. There are 5 address inputs which allows the game to select 1 of 32 different colors for each pixel on the screen. First look at address input A4. It goes through chip 14 to the NOR gate chip 41. The two inputs of the NOR gate are connected to the SH1 and SH2 inputs. If both of these inputs are low then the output of the gate will go high and select colors 16-31 in the palette, otherwise colors 0-15 will be selected. The next two address inputs, A2, A3, come through chip 14 to the OR gates, chip 42. The circuit that generates these two address inputs is actually simpler then it looks. We start with 4 image data inputs, each of which come from a different image bus: 1Y = SH1 Image data from RAM 2Y = SH2 Image data from RAM 3Y = OD1 Image data from graphics ROM 4Y = OD2 Image data from graphics ROM The two OD inputs go to the AND gates in chip 56. The other input of each of each of these gates goes to the NOR gate 41 which we looked at earlier. If either of the SH busses goes high then the AND gates will be disabled thus preventing the OD image data from getting through. This give the SH images priority over the OD images, the SH images will always appear on top of the OD images. The OR gates 42, allow either the SH or OD data to pass onto addresses A2 and A3. The final 2 address bits to the PROM (A0, A1) come through chip 14 to chip 29 which is a multiplexer chip. The data for A0, A1 can come from two sources, the BACK1/2 inputs, and from chip 30. The S input to the mux selects which gets passed to A0,A1. The select input is controlled by the NOR gate 41. Whenever the two bits of image data are both low, the BACK1/2 inputs to the mux are selected, thus selecting a background color. If either of the image data bits is high then the A input of the mux is selected which comes from chip 30. Chip 30 is also a mux chip. It selects either the 1C0/1C1 inputs or the 2C0/2C1 inputs. The selection is controlled by NOR gate 41, so that if an SH image is being displayed 1C0/1C1 is selected, otherwise 2C0/2C1 is selected. 3.5 Putting all together Now that we have looked at all the details of the video system we can put it together into a complete description of how the video system works. We are assuming that the screen on this game is 32x32 characters. The CRT controller generates the address to access the RAM at $400 - $FFF to draw the character at each location on the screen. There are three ranges off address between $400-$FFF and each is 1024 bytes long (1024 = 32x32). Here is the function of each range: $400-$7FF Bit 0..7 = Select character to display $800-$BFF Bit 0..7 = Select Shape to display over current character $C00-$FFF Bit 0,1 = Color Palette select for current SHAPE Image (SH) Bit 2,3 = Color Palette select for current Character Image (OD) Bit 4..7 = Not connected The character ROMS have the following format: Total characters: 256 Size of characters: 8x8 pixels Color bits per pixel: 2 1 bit plane from ROM 73 1 bit plane from ROM 75 The SHAPE RAM is written to at the following addresses: $1000-$13FF = Shape bank 0, Color plane 0 $1400-$17FF = Shape bank 1, Color plane 0 $1800-$1BFF = Shape bank 0, Color plane 1 $1C00-$1FFF = Shape bank 1, Color plane 1 The format of the SHAPE images is the same as the character ROMS except that there are only 128 SHAPE images in each bank. The SHAPE image is selected by the data in $800-$BFF. Bits 0..6 select the image to draw, bit 7 selects which bank to use. There are 32 colors in the color palette, they are setup as follows: 00-15 Shape colors 16-31 Character colors 4.0 Sound (To be added at a later date) Appendix 1: Converting Binary to Hex It will often be necessary to convert from binary to hexadecimal when figuring out address decoding, and other parts of the circuit. This process is actually quite easy: Start with a binary number: 1001111100001010 first, working right to left break it up into 4 bit wide chunks: 1001 | 1111 | 0000 | 1010 Each chunk represents a different hexadecimal digit: 0000 = 0 0100 = 4 1000 = 8 1100 = C 0001 = 1 0101 = 5 1001 = 9 1101 = D 0010 = 2 0110 = 6 1010 = A 1110 = E 0011 = 3 0111 = 7 1011 = B 1111 = F 1001 | 1111 | 0000 | 1010 9 F 0 A So this binary number is $9F0A in hex. The '$' is traditionally used to indicate a hex decimal number. For emulators that are written in C, hex number are proceeded by a '0x'. So in C $9F0A would be typed: 0x9F0A.